I found an article that shows interesting analysis of power savings in a data center. In a 5,000-square-foot data center, a 1-watt reduction at the server-component level (processor, memory, hard disk, etc.) results in an additional 1.84-watt savings in the power supply, power distribution system, UPS system, cooling system, etc. Consequently, every watt of savings that can be achieved on the processor level creates approximately 2.84 watts of savings for the overall facility.
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Tom's Hardware tested the power and performance of current Solid State Disks (SSDs) both in terms of performance and power. While the performance numbers were as expected, it turns out that the flash based drives' energy utilization is no better than a traditional 7200 RPM hard disk for a practical workload based on the MobileMark benchmark. The authors contend that this is because hard disks reach their maximum power draw only when seeking, whereas flash storage uses full power during any IO activity.
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The Barcelona (aka "K10") microarchitecture is the latest design from AMD for both the server and desktop markets. The Phenom is the quad-core desktop variant, the Athlon X2 series includes the dual-core variant, and the 23xx and 83xx Opterons are the quad-core server varient.
The key changes over the previous line are covered in brief here and in greater detail here. Most of the interesting features require the use of an upgraded CPU socket denoted by a "+" (e.g. Socket AM2+ or Socket F+), though the CPU will work in non-plus sockets on current motherboards. Some of the "plus socket" features are:
• Separated voltage planes allow the CPU to have a different voltage/frequency for each core and the northbridge.
• HyperTransport 3.0, allowing greater bus bandwidth, including support for DDR2-1066.
In addition, the Barcelona introduces a shared L3 cache, which should have a major impact on HPC applications.
One major issue, however, is an L3 TLB bug present in the first generation of this architecture. This problem can be solved by disabling part of the L3 TLB system in the BIOS or via software (with a 10% performance penalty), or using a unique Linux patch to route around the problem with limited slowdown (but the patch is not intended for production use). See the Phenom wikipedia article for details.
In short, while Intel retains the upper hand in horsepower now, the AMD Barcelona design seems to sport many of the features predicted for future system design.
More information:
Wikipedia's Barcelona article covers the architecture in depth.
Anandtech benchmarking puts the chip through its paces.
To find a Barcelona-based chip, see Wikipedia:
• Phenom quad-cores
• Barcelona-based dual-core Athlons (scroll to "Phenom based")
• Barcelona-based quad-core Opterons (23xx and 83xx)
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There is some good information about adaptive power management at Berkeley. It appears to be a position statement/paper in construction arguing for power management in data centers.
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This Ars Technica article spotlights the development of power-aware technologies at the chip, system, network, and data center levels. It analyzes recent developments in terms of granularity, i.e. the frequency of reaction. Overall, a well written article.
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This article talks about the performance issues on multi-core system. It basically recommends to use the parallelism, such as OpenMP, in order to take full advantage of it. It also gives the common issues limiting the performance. I think it's a very good article to summarize idea.
http://www.devx.com/go-parallel/Article/34428
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Here are the paper list proposing research using the OpenMP library in Power-aware computing area.
1. Chun Liu, et. al, "Exploiting Barriers to Optimize Power Consumption of CMPs", IPDPS 2005.
This work is to use slack time among processors. By figuring out stall time at the end of each iteration, it reduces the frequency to save power without performance degradation. The evaluation in th paper is done only with simulator, not real experiment. SpecOMP is used to verify the idea.
2. Matthew Curtis-Maury, et. al, "Online Power-Performance Adaptation of Multithreaded Programs using Hardware Event-Based Prediction", ICS 2006.
This paper designed and implemented a framework that can adaptively regulate the concurrency level during program execution. So, the processors/threads configuration is changed based to achieve near-optimal energy efficiency. It build power/performance models and uses the hardware counters. For evaluation, 4 hyperthreaded Intel processors are used.
3. Jian Li, et. al, "Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors", HPCA 2006.
This paper proposes a heuristic method to determine # of processors and frequency level on one CMP node. All evaluation are performed on simulator. It does not expand the approach to multiple CMP nodes.
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By way of slashdot, this Exoid article details how to make sure Windows uses the S3 sleep state, even for an always-on server. Also linked is this handy reference to the possible ACPI sleep states.
Perhaps something like this could be developed into a vehicle for low-utilization servers?
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